1. Field of the Invention
The invention relates to a digital video tape recorder (VTR). More particularly, the invention relates to a digital to analog (D/A) conversion apparatus, a decoder having such D/A conversion apparatus for decoding transmission signals, and a tape drive equipped with such decoder.
2. Description of Related Art
FIG. 1 shows an exemplary tape format for use in a digital video tape recorder (VTR). In track pattern thereof, two video sectors VS and four audio sectors AS are provided on each helical track TR. The four audio sectors AS are disposed between two video sectors VS.
In a conventional VTR, multiple control signals including record enable signals are transferred to devices associated with a rotary drum side via a rotary transformer. The multiple control signals are supplied to the rotary transformer in the form of a serial signal. The devices associated with the rotary drum retrieve the multiple control signals from the serial signal received from the rotary transformer. In order to convert the multiple control signals into the serial signal, use is made of a multiplex (MPX) encoder, and in order to retrieve the multiple control signals from the serial signal, an MPX decoder is used.
In the digital VTR, audio insert requires recording signals in the insert areas provided for audio signal at accurate timing. It is therefore necessary to transfer the control signals such as record enable signal via the MPX encoder and the MPX decoder at accurate timing.
FIG. 2 is an enlarged view of the typical insert area. Provided before and after each insert area are a pre-amble and a post-amble (not shown), respectively. It is noted that if a record enable signal is passed through an MPX encoder and an MPX decoder (hereinafter simply referred to as MPX also), the jitters will result in the record enable signal. The jitters overlap the pre-amble. These jitters depend on the translate cycle of register in the MPX decoder. In order to achieve accurate audio insert, this translate cycle is preferably short.
FIG. 3 shows a serial data format for use with conventional MPX scheme. In the conventional MPX scheme, the data format includes, in addition to 17-bit resister data (DATA), an 8-bit start code (START CODE), 1-bit odd parity (ODD PARITY), 4-bit end code (END CODE), and 8-bit interval (INTERVAL). Each bit of the 17-bit register data is assigned to one control signal.
Thus, in the conventional MPX serial data format, such 21-bit redundancy (start code, odd parity, end code, and interval) should be added to the 17-bit register data, which leads to an encoding rate of 0.5 or less, due to the high redundancy.
Moreover, if the register data has 36 bits, then the redundancy is more than 21-bits for 36-bit register data. Therefore, the conventional MPX serial data format has a drawback in that on account of inevitable increase in redundancy with number of bits the data has, multiple control signals disadvantageously require much too long translate cycle of the register in the MPX decoder, resulting in inefficient data transmission.
FIG. 4 shows a configuration of a conventional MPX encoder 210.
The MPX encoder 210 includes latch circuits 211-1–211-n each for latching a set of 1-bit data D1–Dn as the control signals every translate cycle, a start/end code generation circuit 212 for generating a start code and an end code, a parity generation circuit 213 for generating a 1-bit odd parity every n-bit sets of the register data latched and obtained by the latch circuits 211-1–211-n, and an interval generation circuit 214 for generating an interval.
The MPX encoder 210 also includes a shift register 215 for generating a data sequence for one translate cycle and transmitting each data sequence as the serial data (SERIAL DATA). The data sequence is generated so that the start and end codes generated by the start/end code generator 212, the odd parity generated by the parity generation circuit 213, and the interval generated by the interval generation circuit 214 are added to each set of the n-bit register data sequentially latched and obtained in the latch circuits 211-1–211-n. The MPX encoder 210 further includes a bi-phase encoder 216 for bi-phase encoding the serial data received from the shift register 215 to obtain an output data (DATA OUT).
It is noted that a clock signal CK is supplied to the latch circuits 211-1–211-n, the start/end code generator 212, parity generation circuit 213, interval generation circuit 214, shift register 215, and bi-phase encoder 216 to allow them to be operated on the clock signal CK.
Referring to FIG. 4, operations of the MPX encoder 210 will now be discussed.
Each set of 1-bit data D1–Dn as the control signal is supplied to the latch circuit 211-1–211-n. The latch circuits 211-1–211-n respectively latch the set of the data D1–Dn for each translate cycle. The register data thus latched in the latch circuits 211-1–211-n constitute n-bit parallel data. Such parallel data is sequentially supplied to the shift register 215.
The n-bit data latched and obtained for each one translate cycle in the latch circuits 211-1–211-n is also supplied to the parity generation circuit 213. In the parity generation circuit 213, a 1-bit odd parity is generated on n-bit register data basis. The odd parity thus generated is supplied to the shift register 215.
In the shift register 215, the start and end codes generated by the start/end code generator 212, the odd parity generated by the parity generation circuit 213, and the interval generated by the interval generation circuit 214 are added to each set of the n-bit register data received from the latch circuit 211-1–211-n to form the data sequence for each translate cycle (as shown in FIG. 3).
The shift register 215 serially transmits and supplies each data sequence thus formed to the bi-phase encoder 216 as a serial data. The bi-phase encoder 216 receives and bi-phase encodes the serial data from the shift register 215 to transmit it as serial output data (DATA OUT). The clock signal CK supplied to the respective circuits is also output from the encoder as an output clock signal (CK OUT).
FIG. 5 shows a configuration of a conventional MPX decoder 220. The MPX decoder 220 includes a bi-phase decoder 221 for performing bi-phase decoding on the serial input data (DATA IN) fed thereto to obtain a data sequence for each translate cycle sequentially, and a shift register 222 for shifting each data sequence obtained in the bi-phase decoder 221. The shift register 222 is constituted of a multiplicity of serially connected registers that are respectively associated with, for example, start code (START CODE), register data (DATA), odd parity (ODD PARITY), and end code (END CODE) in the data sequence for each translate cycle.
The MPX decoder 220 also includes a start/end code detection circuit 223 for detecting the start and end codes in the outputs from the registers of the shift register 222, each register corresponding to the start and end codes, and a parity detection circuit 224 for detecting a transmission error in the output from the registers of shift register 222, each register corresponding to the register data and the odd parity.
The MPX decoder 220 also includes latch circuits 225-1–225-n each for latching the outputs of n registers in the shift register 222, each register corresponding to the register data thereof, to obtain a set of data D1–Dn as the control signal, provided that the relevant start and end codes are detected in the start/end code detection circuit 223 and that no transmission error is detected by the parity detection circuit 224.
The MPX decoder 220 further has a D/A converter 226 having a serial interface. Of the sets of data D1–Dn as the control signals transmitted from the latch circuits 225-1–225-n, the data representing the clock signal CK, the data representing strobe signal STROBE, and the data representing input data DATA are supplied to the D/A converter 226. From the D/A converter 226, a multiplicity of analog output signals (D/A OUT) is obtained for controlling, for example, gains of record amplifiers in multiple channels.
The clock signal CK is also supplied to the bi-phase decoder 221, the shift register 222, the start/end code detection circuits 223, the parity detection circuit 224, and the latch circuits 225-1–225-n to allow them to be operated on the clock signal CK. Simply stated, this clock signal CK is the output (CK OUT) of the above MPX encoder 210, supplied therefrom via the rotary transformer.
Referring to FIG. 5, operations of the MPX decoder 220 will be explained below.
Serial input data (DATA IN) is supplied to the bi-phase decoder 221. The input data (DATA IN) is the output data (DATA OUT) issued from the MPX encoder 210 mentioned above via the rotary transformer. The bi-phase decoder 221 bi-phase decodes the input data (DATA IN) to obtain the data sequence for each translate cycle sequentially. Each of the data sequences obtained in the bi-phase decoder 221 is sequentially supplied to, and registered in, the shift register 222.
The start/end code detection circuit 223 receives the outputs of the multiple registers in the shift register 222, each register corresponding to the respective bits of the start and end codes, for detection of the start and end codes. The output of the start/end code detection circuit 223 (referred to as detection signal) is also supplied to the latch circuits 225-1–225-n. The parity detection circuit 224 receives the outputs from multiple registers in the shift register 222, each register corresponding to respective bits of the register data and the odd parity, for detection of a transmission error. The output (detection signal) of the parity detection circuit 224 is supplied to the latch circuits 225-1–225-n. 
The latch circuits 225-1–225-n receives outputs from the n registers in the shift register 222 each register corresponding to respective bits of register data. In the latch circuits 225-1–225-n, the outputs of n registers in the shift register 222, each register corresponding to respective bits of register data, are latched to obtain a set of data D1–Dn as the control signals, provided that the relevant start and end codes are detected in the start/end code detection circuit 223 and no transmission error is detected in the parity detection circuit 224.
It is noted that the latch circuits 225-1–225-n refrains from latching the outputs from the n registers of the shift register 222, each register corresponding to respective bits of register data, when the parity detection circuit 224 detects a transmission error, if the start/end code detection circuit 223 detects the start and end codes. Instead, the latched output by the latch circuits 225-1–225-n in the preceding cycle is held in the latch circuit as it is. In that event, therefore, no register data accompanying a transmission error may be latched in the latch circuits 225-1–225-n, thereby preventing the erroneous set of data D1–Dn from being output as control signals.
Of the sets of data D1–Dn as the control signals available from the latch circuits 225-1–225-n, the data representing the clock signal CK, the data representing strobe signal STROBE, and the data representing input data DATA are supplied to the D/A converter 226. The D/A converter 226 receives the input data DATA and the set of data is sequentially entered in the shift registers therein in synchronism with the clock signal CK.
As will be stated later, such input data DATA is composed of an address data indicative of the channel which the data DATA is associated with and subsequent gain control data for controlling the gain of the record amplifier in the channel specified by the address data as a separate data sequence. At the timing of supplying the strobe signal STROBE (this timing hereinafter referred to as STROBE supply timing), analog output signal (D/A OUT) for controlling the gain of the record amplifier in the channel thus specified by the address data as a prescribed separate data sequence is updated to a value that corresponds to the gain control data contained in the corresponding data sequence.
FIG. 6 shows a configuration of the D/A converter 226. The D/A converter 226 has a shift register 231 for sequentially receiving the input data DATA in synchronism with the clock signal CK. The shift register 231 comprises a multiplicity of serially connected registers each corresponding to portions related to the address data and the gain control data contained in the separate data sequence in the above input data DATA.
The D/A converter 226 also has an address decoder 232 for decoding, at the STROBE supply timing, the outputs of the multiple registers associated with the respective bits of the address data in the shift register 231 and for supplying a latch pulse to selected one of the multi-channel latch circuits 233-1–233-L as described later.
At the STROBE supply timing, the outputs of the registers in the shift register 231, each register corresponding to the respective bits of the address data, constitute the address data within the separate data sequence in the input data DATA. Concurrently, the outputs of the registers in the shift register 231, each register corresponding to the respective bits of the gain control data, constitute the gain control data within the separate data sequence in the input data DATA
The D/A converter 226 also has latch circuits 233-1–233-L, associated with first through Lth channels, respectively, each for latching the outputs of the multiple registers in the shift register 231 as a whole, each registers corresponding to the respective bits of the gain control data. Each of the latch circuits 233-1–233-L receives a latch pulse issued from the address decoder 232, as already stated.
The D/A converter 226 further has D/A conversion sections 234-1–234-L each for converting into respective analog signals the gain control data for the first through Lth channels latched in the latch circuits 233-1–233-L, and buffers 235-1–235-L each for receiving the analog output signals (D/A OUTPUT) from the D/A conversion sections 234-1–234-L and supplying them to the record amplifiers (not shown) associated with the first through Lth channels.
Referring again to FIG. 6, operations of the D/A converter 226 will be described below.
Input data DATA and the clock signal CK are supplied to the shift register 231, where the input data DATA is sequentially registered in synchronism with the clock signal CK.
The outputs of the registers in the shift register 231, each register corresponding to the respective bits of the address data, are supplied to the address decoder 232, while the outputs of the registers in the shift register 231, each register corresponding to the respective bits of the gain control data, are supplied as a whole to the latch circuits 233-1–233-L.
In the address decoder 232, the outputs of the registers in the shift register 231, each register corresponding to the respective bits of the address data of shift register 231, are decoded at the STROBE supply timing. A latch pulse is supplied from the address decoder 232 to a latch circuit at the particular channel specified by the address data, among the latch circuits 233-1–233-L. In the latch circuits that are provided with the latch pulse, the outputs of the registers in the shift register 231, each register corresponding to the respective bits of the gain control data, are latched as a whole.
The gain control data thus latched in the latch circuit for that particular channel is supplied to the D/A conversion section associated with that particular channel among D/A conversion sections 234-1–234-L and converted to an analog signal before it is supplied to the record amplifier of that channel via an associated buffer. In this manner, a gain control data is latched at every STROBE supply timing in the latch circuit associated with that channel specified by the address data, thereby updating the analog output signal D/A OUT for that channel.
FIG. 7 shows a timing diagram illustrating operations of the D/A converter 226. Part “A” of FIG. 7 is indicated in “FIG. 7-(A)”, such representation is used in the following FIGS. 8, 15, 16, and 17. FIG. 7-(A) indicates input data DATA into the D/A converter 226. The input data DATA of separate data sequence consists of 8-bit address data A7–A0 and 8-bit gain control data D7–D0. Such data sequences are sequentially entered into the shift register 231 in synchronism with the clock signal CK as shown in FIG. 7-(B). The gain control data D7–D0 is latched in the latch circuit for the particular channel specified by the address data A7–A0, at time t0 of the STROBE supply timing, as shown in FIG. 7-(C). The analog output signal D/A OUT for that particular channel is then updated as shown in FIG. 7-(D).
If, however, an error is involved in any of the address data A7–A0 and gain control data D7–D0 forming the input data DATA of the separate data sequence, analog output data D/A OUT of a channel other than the particular channel to be updated may be updated and/or a wrong output level could be set as the analog output signal D/A OUT for that particular channel.
FIG. 8 shows a timing diagram illustrating the operations of the D/A converter 226 in a case when an error exists in the gain control data D7–D0. As shown in FIG. 8-(A), when there is an error in the gain control data D7–D0, the incorrect gain control data is entered into the shift register 231 in synchronism with the clock signal CK shown in FIG. 8-(B). Consequently, erroneous gain control data D7–D0 is latched in the latch circuit of the particular channel specified by address data A7–A0 at time t0 of the STROBE supply timing shown in FIG. 8-(C). As a result, the analog output signal D/A OUT of that channel is updated to a wrong level, as shown in FIG. 8-(D).
Thus, the D/A converter 226 of the conventional MPX decoder 220 has a drawback in that, if an error occurs in any of the address data A7–A0 and the gain control data D7–D0 forming an input data DATA of separate data sequence, analog output data D/A OUT of a channel other than the particular channel to be updated may be updated and/or a wrong output level could be set as the analog output signal D/A OUT for that particular channel.
It is, therefore, an object of the present invention to provide D/A conversion apparatus, a decoder having such D/A conversion apparatus for decoding transmission signals, and a tape drive equipped with such decoder wherein even when erroneous input data is supplied to the D/A converter having a serial interface, they prevent an erroneous analog output signal from being output therefrom.